Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. Clamps have been devised to shunt current to ground during excessive voltage peaks.
Some protection clamps employ avalanche diodes such as zener diodes to provide the bias voltage for the base of a subsequent power bipolar junction transistor (BJT).
As one alternative, grounded gate NMOS devices (GGNMOS) have also been used as ESD protection devices. However, GGNMOS devices are not only large, consuming a lot of space on a chip, they also suffer from the disadvantage that they support only limited current densities. The protection capability of an ESD protection device can be defined as the required contact width of the structure required to protect against an ESD pulse amplitude, or, stated another way, as the maximum protected ESD pulse amplitude for a given contact width. Thus, the smaller the contact width for a given ESD pulse amplitude protection, the better.
Silicon-controlled rectifiers (SCR), for instance, provide excellent protection against high current densities during ESD events. One of the advantages of SCR 100 over other ESD protection devices, such as a grounded-gate MOS transistor, is the double injection of carriers, which provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device.
One of the disadvantages of a SCR, however, is that a very large positive voltage, e.g., 50 volts, must be dropped across its nodes before the junction breaks down. As a result, SCRs can not be used to protect devices, such as MOS transistors, that can be permanently damaged by much lower voltages, e.g., 15 volts.
One solution proposed in the past, was to use low voltage silicon controlled rectifiers (LVTSCRs) which are not only smaller but allow the reaching of current densities, after snap back, that are some ten times higher than the current densities of traditionally used grounded gate NMOS devices (GGNMOS), thus increasing the ESD protection capability for CMOS circuits.
However conventional LVTSCRs fail to address yet another concern in designing ESD protection devices, namely the ability to accommodate both positive and negative polarity voltage pulses. Nevertheless a brief overview of the structure and workings of a LVTSCR is useful.
A conventional LVTSCR incorporates a NMOS transistor into the SCR structure. FIG. 1 shows a cross-sectional diagram of a conventional LVTSCR 100. It includes a gate 110 that is formed over channel region 112 and is isolated by a gate oxide layer 114. The channel region 112 is flanked by two n+ regions 116, 118, to define a NMOS transistor.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10–15 volts.
Typically the NMOS transistor is formed to be identical to the to-be-protected MOS transistors. Thus, the junction between n+ region 116 and p-material 120 breaks down at the same time that the to-be-protected MOS transistors experience junction break down as a result of an ESD pulse.
In operation, when the voltage across node 124 (which is connected to the high potential) and node 126 (which is connected to the low potential) is positive and less than the trigger voltage, the voltage reverse biases the junction between n-well 122 and p-type material 120. The reverse-biased junction, in turn, blocks charge carriers from flowing from node 124 to node 126. However, when the voltage across nodes 124 and 126 is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into material 120, and a large number of electrons to be injected into n-well 122. The increased number of holes increases the potential of material 120 in the region that lies adjacent to n+ region 118, and eventually forward biases the junction between material 120 and n+ region 118.
When the increased potential forward biases the junction, a npn transistor defined by the n+ region 118, p-type material 120 and n-well 122 turns on. When turned on, n+ (emitter) region 118 injects electrons into (base) material 120. Most of the injected electrons diffuse through (base) material 120 and are swept from (base) material 120 into (collector) n-well 122 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 122 are then collected by n+ region 130.
A small number of the electrons injected into (base) material 120 recombine with holes in (base) material 120 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 120 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n-well 122 also decrease the potential of n-well 122 in the region that lies adjacent to p+ region 132, and eventually forward bias the junction between p+ region 132 and n-well 122. When the decreased potential forward biases the junction between p+ region 132 and n-well 122, a pnp transistor formed from p+ region 132, n-well 122, and material 120, turns on.
When turned on, p+ emitter 132 injects holes into base 122. Most of the injected holes diffuse through (base) n-well 122 and are swept into (collector) material 120 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 120 are then collected by p+ region 134.
A small number of the holes injected into (base) n-well 122 recombine with electrons in (base) n-well 122 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well 122 as a result of the broken-down reverse-biased junction. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, the holes swept into (collector) material 120 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 118. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 118 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 132 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
Since junction break down occurs before the MOS transistors of the protected circuit experience destructive gate oxide break down, LVTSCR 100 turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors.
However, as mentioned above, one disadvantage of LVTSCR 100 is that it operates only for positive polarity pulses. Ideally a protection device must not only be able to handle the high current densities encountered during an ESD pulse, it must also, in the case of I/O cell protection, accommodate both positive and negative polarity voltage pulses.
The present invention seeks to address this issue.